In bulk CMOS technologies, the mainstream technology of bulk MOSFET has poor scalability beyond semiconductor manufacturing processes of 32 nm and below. To circumvent the poor scalability of the bulk MOSFET, numerous alternatives have been proposed (e.g., fully-depleted (FD) or extremely thin (ET) silicon-on-insulator (SOI) MOSFET, 3D fin field effect transistor (FinFET)). However, each of the alternatives has significant drawbacks. For instance, the FD/ET SOI MOSFET requires expensive wafers with well-controlled thin silicon (tSi) films down to 5 nm resulting in a high series resistance (Rseries). Additionally, the 3D FinFET has a complex integration process, fin variation issues, and also has a high Rseries.
The DDC MOSFET has an improved performance over the bulk MOSFET (e.g., increased mobility, lower threshold voltage (Vt), reduced random dopant fluctuation (RDF), low power, etc.). However, traditional DDC MOSFET technologies require a thermal budget after forming the channel layer in order to achieve adequate dopant fluctuation and diffusion levels. As such, conventional steps (e.g., gate oxide formation, epitaxial source/drain (S/D) pre-bake, S/D rapid thermal anneal (RTA)) limit depleted layer scaling which is necessary for semiconductor manufacturing processes below 10 nm. Additionally, in order to maintain the thermal budget, traditional DDC MOSFET technologies frequently require special low temperature gate oxide growth and low RTA temperatures that adversely impact oxide quality and process capability.
A need therefore exists for methodology enabling formation of an improved DDC MOSFET having minimized dopant fluctuation and diffusion levels, and the resulting device.